This invention relates to a write control circuit for a memory device, and more specifically to a write control circuit adapted for use in a very high-speed semiconductor memory device.
The write operation of a semiconductor memory device is controlled according to a write enable (WE) signal supplied externally. In a conventional high-speed semiconductor memory device, as shown in FIG. 3, the WE signal itself, after amplification by an amplifier-gate 6, is directly applied to sense amplifiers 14.
An improved write control circuit adapted for use in a high-speed semiconductor memory device is disclosed in Electronic Design, Dec. 27, 1984, pp. 157-170. In this circuit, as shown in FIG. 4, the WE signal is latched in a latch 15 by an externally supplied clock signal (CLK). The output of this latch activates a write timing generator 16 whose output signal is applied to the sense amplifiers 14. This timing mechanism not only eliminates many difficulties in the timing of various signals within a high-speed semiconductor memory device but also permits overlapping of input operations and output operations, taking advantages of the capability of forming a read cycle and a write cycle equal in length and timing.
For the conventional circuit shown in FIG. 3, the duration of the WE signal must be shorter than a write cycle. Even for the improved circuit shown in FIG. 4, the duration of the WE signal can not exceed the write cycle. On the other hand, for a very high-speed bipolar or GaAs memory device like those used as a cache memory or a register group in a supercomputer, a very short cycle time, for example a few nanoseconds or so, is required. In a semiconductor memory device which is required to operate at such a very high speed, when mounting conditions are taken into account, it is not easy to control the write operation correctly by means of the WE signal with a duration equal to or shorter than the write cycle, owing to an substantial decrease in pulse duration resulting from waveform deterioration, noises, skews, and the like. Where the pulse duration is exceedingly short, it becomes very difficult to precisely control the timing of the rising or falling edge or the pulse duration.